In the usage of computer systems, and particularly on processor boards, there are large amounts of data which often have to be moved between a processor and the system busses. Normally, the amount of printed circuit board real estate available will be at a minimum, while however, the gate count to implement the functions will be of a very high number. Generally the best solution for involvement here, is usually a custom gate array. However the development costs involved therein are usually very high and the gate array must be tailored to the specific application involved.
There is always a design risk associated in the development of a gate array within a system design. The greatest danger is that a fatal error will be discovered within the gate array somewhat late in the design cycle, thus necessitating a recycle, redesign and thus delaying the production schedule.
In order to alleviate this problem, it is desirable to design a gate array so that the danger of a design error within it is very low. In past technology, some gate array designs have had hooks built into them to allow controls to disable portions if an error was discovered during the debug operation.
While this is a desirable action, it required much effort to be extended to implement these functions which also themselves contain a chance for error. The optimum way to solve problems of this sort is to provide a data path that moves and holds data only, while all of the routing and loading controls are implemented in programmable logic outside of the gate array. By using a very simple design, the chances of implementation errors or design errors are reduced to a very low probability.
In the design function, it is most desirable to create a design that is not tightly coupled with a particular system being used. The main benefit of this is that the cost of producing the gate array will be lower as the development costs are spread over a number of useful devices. Additionally it is easy to target the data path architecture to new gate array technologies as incremental improvements are made. This enables designers to lower the development costs and thus speeds up the schedule of any subsequent projects which use the adaptable data path gate array.
In the design process, it is also desirable to create a design that is testable and can also support diagnostics used elsewhere on the printed circuit boards. This can be accomplished by having all flip-flops in the system on a shift chain so the "state" of each circuit or circuit elements can be examined during diagnostics, or additionally, data can be loaded into any register within the gate array. By using boundary scan techniques, the state of all inputs to the array can be examined, as well as allowing any desired value to be driven out of the array to facilitate testing. Further, it is desirable that parity checking and parity generation should be included in the system to insure data integrity throughout the gate array.